View MB86292PFFS-G-BND_604582.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

FUJITSU SEMICONDUCTOR DATA SHEET
DS04-31103-1E
ASSP for Graphics Control
Graphics Display Controller MB86292
s DESCRIPTION
The MB86292 is an evolved version of the Fujitsu MB86290A graphics controller designed for use in a car navigation system or amusement equipment. The MB86292 is a graphics display controller with an on-chip geometry processor and digital video capture facility. It can be connected to FCRAM. Connecting the MB86292 to FCRAM which has lower latency upon a paging error speeds up the random access to memory, resulting in faster display and drawing. In addition, integrating the geometry processor reduces the CPU load, thereby improving the performance of the entire system.
s FEATURES
* Operating frequency : 100 MHz (External clock of 14.32 MHz Max) * Geometry processor : Capable of executing operations for geometric transformation and surface front/rear evaluation. * Memory block : Capable of connecting SDRAM and FCRAM * Video capture block : Embedded facility to capture digital video images, for example, from TV, capable of easily implementing "Picture in Picture" and video graphics superimposing. * Host interface : Enables direct connection to various CPUs (Fujitsu SparcLite, Hitachi SH3/4 or NEC V83x) . (Continued)
s PACKAGE
256-pin plastic QFP
(FPT-256P-M09)
MB86292
(Continued) * Drawing features : * Drawing at a peak rate of 800 Mpixel/s (at an internal operating frequency of 100 MHz) * 2D drawing functions : Point, line, triangle, polygon, BLT and pattern drawing * 3D drawing functions : Point, line, triangle drawing and hidden surface removal by Z-buffering * Special effects : Anti-aliasing, bold/dashed-line processing, alpha blending, Gouraud shading, texture mapping (bilinear filtering, perspective correct) , and tiling * Display features : * Maximum display resolution supported : 1024 x 768 pixels * Color display either with a color palette of 8 Bit/Pixel or directly using 5-bit RGB colors of 16 Bit/Pixel * Overlaying four layers of screen, of which two lower layers can be divided into the left and right parts * Supporting two 64 Pixel x 64 Pixel hardware cursors * Output of analog RGB and digital RGB signals * Capable of superimposing using an external synchronization mode * Power-supply voltage : Two power supplies at 2.5 0.2 V, for internal circuits and 3.3 0.2 V for I/O parts * Package : PlasticQFP with 256 pins (with a lead pitch of 0.4 mm) * Process technology : CMOS 0.25 m
2
MB86292
s PIN ASSIGNMENT
CS BS RD RESET VSS VDDL VDDH DTACK/TC DRACK/DMAAK A24 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 VSS VDDL A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VSS VDDH OSCCNT PLLVDD S OSCOUT PLLVSS CLK VSS VDDL CLKSEL0 CLKSEL1 CKM VI7 VI6 VI5 VI4 VI1 VI0 VI3 CCLK VI2 VSS VDDL VDDH DCLKI TESTH TESTH TESTH TESTH
(TOP VIEW)
WE0 WE1 WE2 WE3 BCLKI MODE0 MODE1 MODE2 TESTH TESTH VDDH VDDL VSS RDY DREQ INT D0 D1 D2 D3 D4 D5 VDDH VSS VDDL D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 VSS VDDL D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 VDDH VDDL VSS MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 203 205 202 204 201 200 199 188 187 186 185 184 183 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129
TESTH GV VSYNC HSYNC CSYNC DISPE DCLKO VDDH VSS VDDL R7 R6 R5 R4 R3 G7 G6 G5 G4 G3 B7 B6 B5 B4 B3 VSS VDDL VDDH MD63 MD62 MD61 MD60 MD59 MD58 MD57 MD56 MD55 MD54 MD53 MD52 MD51 MD50 MD49 MD48 VSS VDDL MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 VSS VDDH
VSS/PLLVSS VDDH VDDL/PLLVDD PLLVDD OPEN TESTH
Notes : * The PLLVDD should be separated on the board. * Insert a bypass capacitor with a superior high-frequency characteristic between the power supply and ground. Place the capacitor as near the pins as possible. 3
VDDL VSS MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 VDDH VDDL VSS MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MA0 MA1 MA2 MA3 MA4 VDDH VSS MCLKO MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MWE VDDH VDDL VSS MDQM0 MDQM1 MDQM2 MDQM3 MDQM4 MDQM5 MDQM6 MDQM7 MRAS MCAS VDDL VSS MCLKI RGBEN
: Ground : 3.3 V power supply : 2.5 V power supply : PLL power supply : Do not connect anything. : Input the high level.
MB86292
s PIN DESCRIPTION
D0-D31 A2-A24 BCLKI RESET CS RD WE0-WE3
DCLKO DCLKI HSYNC VSYNC CSYNC DISPE GV R3-R7 MB86292 Graphics Controller G3-G7 B3-B7 RGBEN HQFP256 CCLK VI0-VI7
Video output interface
Host CPU interface
RDY BS DREQ DRACK DTACK INT MODE0-MODE2 TESTL, TESTH
Vide capture interface
CLK S
MD0-MD63 MA0-MA13 MRAS MCAS MWE MDQM0-MDQM7 MCLKO MCLKI
Clock
CKM CLKSEL0CLKSEL1 OSCOUT OSCCNT
Graphics memory interface
4
MB86292
* Host Interface Pins Pin Name Input/output MODE0MODE2 RESET D0-D31 A2-A24 BCLKI BS CS RD WE0 WE1 WE2 WE3 RDY DREQ DRACK/ DMAAK DTACK/TC INT TESTH Input Input Input/output Input Input Input Input Input Input Input Input Input Output Tristate Output Input Input Output Input
Function Host CPU mode/Ready mode select Hardware reset Host CPU bus data Host CPU bus address (Connect A24 to MWR in V832 mode.) Host CPU bus clock Bus cycle start signal Chip select signal Read strobe signal D0-D7 write strobe signal D8-D15 write strobe signal D16-D23 write strobe signal D24-D31 write strobe signal Wait request signal ("0" for wait state with SH3; "1" for wait state with SH4, V832, or SPARClite) DMA request signal (active low with both SH and V832) DMA request acknowledge signal (Connect this to DMAAK in V832 mode. Active high with both SH and V832.) DMA transfer strobe signal (Connect this to TC in V832 mode. SH = active high, V832 = active low) Host CPU interrupt signal (SH = active low, V832 = active high) Test signal
Note : The host interface can connect the MB86292 to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd. the V832 from NEC, or to the SPARClite (MB86833) from Fujitsu without any external circuit in between. (Using the SRAM interface allows the MB86292 to use another CPU.) The host CPU is set by the MODE0 and MODE1 pins as shown below. MODE1 pin L L H H MODE0 pin L H L H SH3 SH4 V832 SPARClite CPU Type
Note : The MODE2 pin can be used to set the Ready signal level to be used upon completion of the bus cycle. To use the MODE2 signal at "H" level, set the software setting to two cycles. MODE2 pin L H Ready signal mode Set RDY signal to "Not Ready" level upon completion of bus cycle. Set RDY signal to "Ready" level upon completion of bus cycle.
5
MB86292
Notes : * The host interface transfers data signals at a fixed width of 32 bits. * There are 23 lines for address signals handled in double words (32 bits) and 32 Mbytes of address space. * The external bus can be used at an operating frequency of 100 MHz maximum. * The RDY signal at the low level sets the ready state in the SH4 or V832 mode; the signal at the low level sets the wait state in the SH3 mode. Note that the RDY signal is a tristate output signal synchronized to the rise of BCLKI. * The host interface supports DMA transfer using an external DMA controller. * The host interface generates a host processor interrupt signal. * The RESET pin requires low level input of at least 300 s after setting "S" (PLL reset signal) to high level. * Fix the TEST signal at high level. * In the V832 mode, connect the following pins as specified : ORCHID Pin Name V832 Signal Name A24 DTACK DRACK MWR TC DMAAK
* Video Output Interface Pins Pin Name Input/output DCLKO DCLKI HSYNC VSYNC CSYNC DISPE GV R3-R7 G3-G7 B3-B7 RGBEN Output Input Input/output Input/output Output Output Output Output Output Output Input Display dot clock signal output Dot clock signal input
Function
Horizontal sync signal output Horizontal sync signal input in external synchronization mode Vertical sync signal output Vertical sync signal input in external synchronization mode Composite sync signal output Display effective period signal Graphics/video select signal Digital video (R) signal output Digital video (G) signal output Digital video (B) signal output RGB2-0 output/memory bus (MD63-55) select signal
Notes : * The video output interface outputs RGB pieces of five-bit display data by default. It can output RGB pieces of eight-bit display data depending on conditions. R0-2, G0-2, and B0-2 can be output to MD61-MD63, MD58-MD60, and MD58-MD60, respectively, by fixing RGBEN to 0. When eight-bit RGB output is selected, only the 32-bit memory bus width mode can be used. * Using an additional external circuit, the video output interface can generate composite video signals. * The video output interface can provide display synchronized with external video. The mode for synchronization with the DCLKI signal can be selected as well as the mode for synchronization with a set dot clock as for normal display. * The HSYNC and VSYNC signals must be pulled up outside the LSI as they enter the input state upon reset. * The GV signal serves to switch between graphics and video for chroma keying. The pin outputs a low level signal to select video.
6
MB86292
* Video Capture Interface Pins Pin Name Input/output CCLK VI0-VI7 Input Input Digital video data input
Function Digital video input clock signal input
Note : The video capture interface inputs digital video signals in the ITU-RBT-656 format. * Graphics Memory Interface Pins Pin Name Input/output MD0-MD54 MD55-MD63 MA0-MA13 MRAS MCAS MWE MDQM0-MDQM7 MCLKO MCLKI Input/output Input/output Output Output Output Output Output Output Input Graphics memory bus data Graphics memory bus data or RGB0-RGB2 output Graphics memory bus data Row address strobe Column address strobe Write enable Data mask Graphics memory clock output Graphics memory clock input
Function
Notes : * The graphics memory interface connects the MB86292 to the external memory used for graphical image data. The interface can directly accept 128-Mbit SDRAM or 64-Mbit SDRAM (with a 16-bit or 32-bit data bus) without any external circuit. * Memory bus data can be selected between 64 bits and 32 bits. To use 32-bit data, leave the MD32-MD63 and MDQM4-7 pins open in the eight-bit RGB output mode (RGBEN pin = 0) or the MD32-MD54 and MDQM4-7 pins open in the eight-bit RGB output mode (RGBEN pin = 0). * Connect the MCLKI pin to the MCLKO pin. * When RGBEN is fixed to 1, MD55-MD63 can be used as graphics memory bus data. When RGBEN is fixed to 0, RGB0-2 is output. * Clock Input Pins Pin Name Input/output CLK S CKM CLKSEL [1 : 0] OSCOUT*1 OSCCNT*
2
Function Clock input signal PLL reset signal Clock mode signal Clock rate select signal For connection of crystal oscillator (Reserved) Crystal oscillator select pin (Reserved)
Input Input Input Input Input/output Input
*1 : Do not connect anything. *2 : Input the "H" level. Notes : * The clock input block inputs the clock signal that serves as the basis for the reference clock for the internal operating clock and display dot clock. Usually input 4 Fsc ( = 14.31818 MHz for NTSC). The internal PLL generates the internal operating clock signal of 100 MHz and the display reference clock signal of 200 MHz. * The internal operating clock signal to be used can be selected between the clock signal (100 MHz) generated by the internal PLL and the bus clock BCLKI input to the host CPU interface. Select the BCLKI input to use the host CPU bus at 100 MHz. 7
MB86292
CKM L H Select internal PLL output.
Clock Mode Select host CPU bus clock (BCLKI).
* Use the CLKSEL pin to select the input clock frequency for using the internal PLL with CKM = L. Display reference CLKSEL1 CLKSEL0 Input Clock Frequency Multiplier clock L L H H L H L H Input 13.5 MHz. Input 14.32 MHz. Input 17.73 MHz. Reserved x 15 x 14 x 11 202.5 MHz 200.48 MHz 195.03 MHz
Note : Immediately after turning the power supply on, input a pulse whose low level period is 500 ns or more to the S pin before setting it to high level. After the S signal goes high, input the RESET signal at low level for 300 s or more.
8
MB86292
s BLOCK DIAGRAM
External Bus of Host CPU
D0-D31 Host Interface A2-A24 Pixel Bus Capture Controller RBT656
Display Controller
DRGB
MD0-MD63 SDRAM or FCRAM External Memory Controller Geometry Engine 2D/3D Rendering Engine
MA0-MA13
9
MB86292
s FUNCTION BLOCKS
* Host Interface This block allows the MB86292 to be connected to the SH3 or SH4 microprocessor from Hitachi Ltd., the V83x microprocessor from NEC, or to the SPARCLite from Fujitsu without any external circuit in between. The block provides an interface to transfer display list and texture pattern data directly from main memory to this device's graphics memory or internal register using the external DMA controller. * External Memory Controller This block connects external SDRAM or FCRAM. The data bus can be selected between 64 bits and 32 bits and the maximum operating frequency is 100 MHz. * Display Controller This block contains a three-channel, eight-bit D/A converter to output analog RGB signals. The block has eightbit RGB digital video outputs, allowing an external digital video encoder to be connected. The block supports resolutions of up to XGA (1024x768 pixels), enabling flexible setting. * Set-up Engine The on-chip geometry engine executes mathematical operations required for graphics processing precisely using the fronting-point format. The geometry engine executes the required geometry processes selected depending on the drawing mode and primitive type settings up to the final drawing process. * 2D/3D Rendering Engine This block draws images in two or three dimensions. 2D drawing The block provides the anti-aliasing and alpha blending functions to display high-quality images even on a lowresolution LCD. 3D drawing The block provides true 3D drawing functions such as perspective texture mapping and Gouraud shading.
10
MB86292
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Output current Power pin current Ambient storage temperature * : The PLL power supply is included. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Symbol VDDL* VDDH VI IO IPOW Tstg Rating Min - 0.5 - 0.5 - 0.5 - 13 60 - 55 Max 3.0 4.0 VDDH + 0.5 ( < 4.0) + 13 60 + 125 Unit V V mA mA C
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Input voltage ("H" level) Input voltage ("L" level) Ambient operating temperature * : The PLL power supply is included. Notes : * The VDDL and VDDH power supplies can be turned on or off in either order. Note, however, that the VDDH voltage must not be applied alone continuously for several seconds. * Do not input the HSYNC, VSYNC, or EO signal with the power-supply voltage not applied. (See "Input voltage" in "s ABSOLUTE MAXIMUM RATINGS".) * After turning the power on, input a pulse remaining at low level for at least 500 ns to the S pin. Then, set the S pin to high level and input the RESET signal held at low level for at least 300 s. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. Symbol VDDL* VDDH VIH VIL TA Value Min 2.3 3.0 2.0 - 0.3 - 40 Typ 2.5 3.3 Max 2.7 3.6 VDDH + 0.3 + 0.8 + 85 Unit V V V C
11
MB86292
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Paramater Output voltage ("H" level) *1 Output voltage ("L" level) *2 Output current ("H" level) (VDDL = 2.5 0.2 V, VDDH = 3.3 0.3, VSS = 0.0 V, Ta = 0 C to + 70 C) Value Symbol Unit Min Typ Max VOH VOL IOH1* IOH2*
3 4
VDDH - 0.2 0.0 - 2.0 - 4.0 - 8.0 2.0 4.0 8.0

VDDH 0.2
V V mA
IOH3*5 IOL1*3 Output current ("L" level) Input leakage current Pin capacitance IOL2* IOL3* IL C
4 5

5 16
mA A pF
*1 : Value when -100 A current flows into output pins. *2 : Value when 100 A current flows into output pins. *3 : Output characteristics of the MD0-63 and MDQM0-7 signal. *4 : Output characteristics of the signals other than those in *3 and *5 *5 : MCLKO signal output characteristics
12
MB86292
2. AC Characteristics
* Input measurement conditions
tr VIH 80% 80% (VIH + VIL) / 2 20% VIL 20% tf
(VIH = 2.0 V, VIL = 0.8 V)
Input
* tr, tf 5 ns * Input measurement standard : (VIH + VIL) / 2
* Output measurement conditions
VIH
Input
VIL
tpHL, tpZL
(VIH + VIL) / 2
tpLH, tpZH
VOH
Output 1
VDD/2 VDD/2
VOL
tpLZ
Output 2
0.5 V
VOL
tpHZ
VOH
Output 3
0.5 V
* Output measurement standard : tpLZ : VOL + 0.5 V tpHZ : VOH - 0.5 V Else : VDD/2 13
MB86292
(1) Host Interface * Clock Parameter BCLKI frequency BCLKI H period BCLKI L period * Host interface signals Parameter Address setup time Address hold time BS setup time BS hold time CS setup time CS hold time RD setup time RD hold time WE setup time WE hold time Write data setup time Write data hold time DTACK setup time DTACK hold time DRACK setup time DRACK hold time Read data delay time (to RD) Read data delay time RDY delay time (to CS) RDY delay time INT delay time DREQ delay time MODE hold time * : Hold time for reset cancellation Symbol Condition tADS tADH tBSS tBSH tCSS tCSH tRDS tRDH tWES tWEH tWDS tWDH tDAKS tDAKH tDRKS tDRKH tRDDZ tRDD tRDYDZ tRDYD tINTD tDRQD tMODH * (Operating condition : External load of 20 pF) Value Unit Min Typ Max 3.0 1.0 3.5 0.0 3.5 0.0 3.0 0.0 5.5 0.0 3.5 0.0 3.5 0.0 4.0 0.0 2.5 4.0 2.0 2.5 2.5 2.5 8.5 10.5 6.0 6.5 7.0 6.5 20.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol fBCLKI tHBCLKI tLBCLKI Condition Value Min 1 1 Typ Max 100 Unit MHz ns ns
14
MB86292
* Clock
1/fBCLKI tHBCLKI tLBCLKI
BCLKI
* Input setup and hold times
BCLKI
A2~A24, BS, CS, D0~D31, DTACK, DRACK
tADS, tBSS, tCSS, tWDS, tDAKS, tDRKS tADH, tBSH, tCSH, tWDH, tDAKH, tDRKH
* Read/write enable (RD, WE) setup and hold times
BCLKI
BS
CS
tRDS, tWES
RD, WE, A24 (MWR)
tRDH, tWEH
15
MB86292
* DREQ/INT output delay time
BCLKI
DREQ (output) INT (output)
tDRQD, tINTD
* RDY delay value (with respect to CS)
BCLKI
CS
High-Z RDY (output)
tRDYDZ tRDYDZ
High-Z
16
MB86292
* RDY, D output delay values (The D pin outputs effective data from the RDY assert cycle.)
BCLKI
RD (CS)
tRDD tRDDZ tRDDZ
D0~D31 (output)
High-Z
output data
High-Z
RDY
tRDYD tRDYD
* MODE signal hold time
RESET
MODE0~ MODE2
tMODH
17
MB86292
(2) Video Interface * Clock Parameter CLK frequency CLK H period CLK L period DCLKI frequency DCLKI H period DCLKI L period DCLKO frequency * Input signals Parameter HSYNC input pulse width HSYNC input setup time HSYNC input hold time VSYNC input pulse width Symbol Condition tWHSYNC0 tWHSYNC1 tSHSYNC tHHSYNC tWHSYNC1 *1 *2 *2 *2 Value Min 3 3 10 10 1 Typ Max Unit clock clock ns ns HSYNC cycle Symbol Condition fCLK tHCLK tLCLK fDCLKI tHDCLKI tLDCLKI fDCLKO Value Min 25 25 5 5 Typ 14.318 Max 67 67 Unit MHz ns ns MHz ns ns MHz
*1 : Applied only in PLL synchronization mode (CKS = 0) . The reference clock is the internal PLL's output with Cycle = 1/ (14 fCLK) . *2 : Applied only in DCLKI synchronization mode (CKS = 1) . The reference clock is DCLKI. * Output signals Parameter RGB output delay time DISPE output delay time HSYNC output delay time VSYNC output delay time CSYNC output delay time GV output delay time Symbol Condition tRGB tDEO tDHSYNC tDVSYNC tDCSYNC tDGV Value Min 2 2 2 2 2 2 Typ Max 10 10 10 10 10 10 Unit ns ns ns ns ns ns
18
MB86292
* Clock
1/fCLK tHCLK tLCLK
CLK
VIH VIL
* HSYNC signal setup and hold
1/fDCLKI tHDCLKI tLDCLKI
DCLKI
HSYNC (input)
tSHSYNC tHHSYNC
* Output signal delay
DCLKO
R7-R3, G7-G3, B7-B3, MD63-MD55*, HSYNC (output), VSYNC (output), CSYNC, GV
*: Valid if RGBEN = 0 tRGB, tDEO, tDHSYNC, tDVSYNC, tDCSYNC, tDGV
19
MB86292
(3) Graphics Memory Interface * Clock Parameter MCLKO frequency MCLKO H period MCLKO L period MCLKI frequency MCLKI H period MCLKI L period MCLKI delay to MCLKO Symbol Condition fMCLKO tHMCLKO tLMCLKO fMCLKI tHMCLKI tLMCLKI tOID Value Min 1.0 1.0 1.0 1.0 0.0 Typ Max * * 3.5 Unit MHz ns ns MHz ns ns ns
* : In BUS asynchronous mode, the frequency is half the internal PLL oscillation frequency. In Bus synchronous mode, the frequency is the same as BCLKI. * Input/output signals Parameter MA, MRAS, MCAS, MWE setup time MA, MRAS, MCAS, MWE hold time MDQM data setup time MDQM data hold time MD output data setup time MD output data hold time MD input data setup time MD input data hold time Symbol Condition tMADS tMADH tMDQMDS tMDQMDH tMDODS tMDODH tMDIDS tMDIDH *1 *1 *1 *1 *1 *1 *2 *2 Value Min 3.2 1.3 3.2 1.3 3.2 1.3 3.0 1.0 Typ Max Unit ns ns ns ns ns ns ns ns
*1 : Setup/hold time with respect to MCLKO *2 : Setup/hold time with respect to MCLKI
20
MB86292
* Clock
1/fMCLKO, 1/fMCLKI tHMCLKO, tHMCLKI tLMCLKO, tLMCLKI
MCLKO, MCLKI
* Input signal setup and hold times
MCLKO
MD0~MD63
Input data
tMDIDS
tMDIDH
* MCLKI signal delay
MCLKO
MCLKI
tOID
* Output signal delay
MCLKO
MA0~MA13, MRAS, MCAS, MWE, MD0~MD63, MDQM0~MDQM7
tMADS, tMDODS, tMDQMDS tMADH, tMDODH, tMDQMDH
21
MB86292
(4) PLL Standards Parameter Input frequency Output frequency Duty ratio Jitter Value Min 101.3 % 180 ps Typ 14.31818 MHz Max 200.45452 MHz Multiplied by 14 93.1 % - 150 ps PLL output clock H/L pulse width ratio Cycle difference between two consecutive cycles Remarks
22
MB86292
s ORDERING INFORMATION
Part Number MB86292PFFS-G-BND Package 256-pin plastic QFP (FPT-256P-M09) Remarks
23
MB86292
s PACKAGE DIMENSION
256-pin plastic QFP (FPT-256P-M09) *Pins width and pins thickness include plating thickness.
30.600.20(1.205.008)SQ 28.000.10(1.102.004)SQ
156 105
0.1450.055 (.006.002)
157
104
0.08(.003)
Details of "A" part 3.730.30 (Mounting height) (.147.012)
INDEX 0~8
208 53
0.40 -0.15
+0.10 +.004
.016 -.006 (Stand off)
"A" LEAD No.
1 64
(0.50(.020))
M
0.25(.010)
0.40(.016)
0.180.05 (.007.002)
0.07(.003)
0.600.15 (.024.006)
C
2000 FUJITSU LIMITED F256025S-c-2-2
Dimensions in mm (inches)
24
MB86292
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0203 (c) FUJITSU LIMITED Printed in Japan

▲Up To Search▲

Price & Availability of MB86292PFFS-G-BND

	To Download MB86292PFFS-G-BND Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .